Fixing a 50GHz Sampling Scope (Tektronix CSA803)

About a month ago I found a rather nice-looking Dell laptop being thrown away on the Stata loading dock, through which the majority of MIT’s tech trash passes. Knowing me to be a scope junky (I currently own 10), a friend quickly offered to trade me an old Tektronix sampling mainframe he’d found that was failing a POST test for my new laptop (in unknown condition), so of course I accepted. Who needs computers when there’s interesting test equipment to be had!

Upon closer examination, the scope (Tektronix CSA803) came with an SD-26 dual-20GHz sampling head installed and was throwing error E5322 on power up. Here’s the unhelpful documentation of the error from Tektronix (translation: “we don’t support this product, we don’t publish a service manual with detailed troubleshooting instructions like we used to, and we want you to buy a new Tek scope”), and here’s a great Google Group thread that has a real solution. It turns out that error E5322 indicates an issue communicating with a pair of battery-backed RAMs on the timebase board, and replacement parts are available from Digikey for about 15 bucks a piece! Win.

A few days later, after the parts had arrived, I pulled the thing apart to get a closer look:

The replacement RAMs are the tall ST chips visible in the top right, U500 and U511.

The replacement RAMs are the tall ST chips visible in the top right, U500 and U511.

Beautiful!

Probing between the power pins on the RAMs confirmed that the battery backups were dead. After replacing them with the new parts, the scope powered up and passed POST. Here’s a measurement of the 1ns risetime of the output clock waveform (this scope has both a calibrator output and internal clock output):

CSA803 Self Cal Test

With the scope working, I decided to buy an SD-24 dual-20GHz sampling head with TDR, extending the scope to 4 channels at 20GHz each, and adding a pair of TDR inputs/outputs. The TDR outputs are capable of generating risetimes as fast as 17.5ps, the idea is that instead of using a network analyzer (which I don’t have) to characterize some system, I can hook up one TDR channel to port 1 and the other to port 2, and then record the step responses on both channels to a step applied to either channel (that’s four measurements, each corresponding to one of the four 2-port S-parameters).

Here’s a shot of the reflected signal from an open termination (nothing connected to the TDR pulse output channel). Looks about right!

Yes, that 7000-series Tek Cart was *definitely* intended for this purpose.

Yes, that 7000-series Tek Cart was *definitely* intended for this purpose.

Translating to frequency domain should then be fairly straightforward: send the data to a computer over RS-232, import into MATLAB, take the derivative to find the impulse response, and then calculate the Fourier transform and scale it appropriately.

Next up, building some high speed probes to make this thing useful.

6.111 or: How I Learned to Stop Worrying and Love the FPGA

So it’s that time of the year again when classes end and I can take a break and write a blog post again!

This semester I took 6.111: “Introductory Digital Systems Laboratory”, aka MIT’s FPGA lab, and produced a functional 2-channel 100MSPS, 25MHz analog bandwidth digital oscilloscope for my final project:

The Analog Front End Board.

The Analog Front End Board.

Half the project was designing and debugging a 4-layer analog front end and sampling board, and the other half was writing the Verilog code to make the thing work. The board layout looks like this (layer is 2 a continuous ground plane that is hidden):

Lots of squiggles!

Lots of squiggles!

The FPGA I used was a Spartan 6 on a Digilent Atlys dev board. The Atlys was chosen due to its HDMI output capability and high speed 68-pin VHDCI connector that was used to interface with the custom front end board. The HDMI output was used to drive an OEM 13.3″ replacement laptop screen I found on eBay and hooked up to an HDMI to 40-pin LVDS controller:

A trace!

A trace!

The front end board contains a pair of TI ADC08200 ADCs that are clocked from the FPGA through a clock buffer IC. My code currently runs them at 100MSPS, but they’re rated for operation up to 200MSPS (potentially doubling the bandwidth of the scope to 50MHz). The ADCs’ reference voltage is set by an AD7801 parallel DAC, which, in addition to a switchable input attenuator, allows for different vertical scales. A few high speed opamps per channel buffer, scale, and offset the input signal (taken from a real scope probe!) into the somewhat narrow input range of the ADCs. Here’s: the schematic. My first trace was acquired with the analog processing bypassed and a signal generator feeding the ADC input directly:

Atlys + HDMI + Front End Board + Sig Gen

Atlys + HDMI + Front End Board + Sig Gen

Sadly enough, I forgot to decouple the opamps to ground (they were only decoupled from V+ to V-). When I first powered the analog processing section, the opamps oscillated and I measured 80mV of input offset voltage in one of the preamplifier stages, which was causing the output the drop outside of the input range of the ADCs. Adding decoupling capacitors from V+ to ground and V- to ground fixed the offset voltage problem and reduced some of the oscillations (remember: the input from the scope probe is referenced to ground, not V+ or V-!). Based on some advice from a friend who knows about fast analog things, I added some input pulldown resistors to one of the opamp stages in each channel, which reduced the effect of parasitic capacitances that can couple the output back into the noninverting input and create oscillations, and I got a trace with input from an oscilloscope probe. Here’s what that looked like:

Oops!

Oops!

Here’s: my final report (warning: big file!) for those that may be interested. Note that this was written in one all-nighter, the night after the all-nighter in which I got the last bits of the project working in time for the checkoff, so reader beware.

I’ll be working on adding more features like simultaneous display of both channels, better interpolation and horizontal scaling, and cursors and measurements in time to present this project at Techfair, so stay tuned for more updates! If time permits, I might even try making a new front end board with 1GSPS ADCs and a variable gain amplifier instead of a switched relay attenuator. Texas Instruments was generous enough to overnight all the ICs I used in this project that they manufacture after I entered their Analog Design Contest, so I might as well continue to make nicer boards… 🙂